Clock Recovery Settings to Generate An Open Eye

Question:  I am evaluating a system that implements SSC to reduce EMI.  However, I cannot generate an open eye or get meaningful results, yet the system is working fine.  It is a 6Gb/s system and I am using the settings of 1MHz loop BW and Type I PLL.

Answer:  These are default CDR settings and may not match your device.  Ideally, you should ask your CDR vendor what specific loop BW and PLL type they are using.  If that is not possible, you should use the minimal settings that are described in the standards document for the specific technology and speed you are implementing.  Here are some rules of thumb if neither of the options above are available:  There are numerous implementations where the loop BW is set to the “golden PLL” of bitrate/1667.  Another rule of thumb is that when deploying SSC, a 2nd order PLL is often used in the CDR system due to the more demanding tracking requirements.  Finally, try increasing the loop BW beyond the “golden PLL” to determine correlation to the specific CDR implementation.

Also (and on a completely separate topic), I’m proud of my new Guest Blog at EDN, just introduced today. Come visit Scope Guru on Signal Integrity!

Explore posts in the same categories: Ask Scope Guru Q/A, High Speed Buses

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